In my U.S. Pat. No. 4,185,275 issued Jan. 22, 1980, I disclosed a multi-stage digital-to-analog converter which employs a sampling capacitor for each stage of coding. In that disclosure, a reference terminal of the sampling capacitor is connected to a tap of a precision resistive divider to provide a binary-weighted reference voltage for a stage, and the other terminal of the sampling capacitor receives the input sample to be quantized by the stage. The analog sample applied to the stage is compared to the reference voltage for the stage and when the input sample is larger than the reference voltage a flip-flop is set for the stage and the reference terminal of the sampling capacitor is disconnected from the reference tap and clamped to ground to "subtract" an increment from the sample. When the voltage of the input analog sample is lower than the reference voltage, the flip-flop is not set and the reference terminal of the capacitor is not clamped to ground. In either event, the input terminal of the sampling capacitor is then connected to the input of the next stage where the process is repeated, except that the reference terminal of the second stage's capacitor is connected to a tap of the resistive divider having a lower binary-weighted reference voltage.
While the foregoing circuit is satisfactory for many applications, it would be advantageous to employ integrated CMOS or NMOS technology, and in these technologies it is difficult to provide a precision resistive divider.
The precision resistive voltage divider is eliminated in my copending application, Ser. No. 504,900 filed June 16, 1983, by the use of a switched capacitor divider network. Positive and negative "binary weights" are developed at each stage in the division process and selection of either the positive or negative bit weight at a stage allows a binary fraction to be added or subtracted.
As with the coder of my previously cited patent, the number of stages in the coder of my copending application advantageously need only be equal in number to the number of desired digit positions in the output. This is in contrast to the present practice where one comparator is required for each quantizing level. The stages are arranged to operate in a "wave" or "pipeline" sequence under the control of a plurality of high speed waveforms so that each stage decodes its respective binary digit for one analog sample while the other stages are decoding their respective binary digits of other analog samples. The result is that in each clock period each capacitor is gainfully employed in the encoding process, yielding a very fast encoder that is suitable for video applications.
While the invention disclosed in my above-mentioned copending application is very useful and has numerous advantages over the prior art in addition to the ones described above, it does require a comparator and a number of capacitors for each stage.
In my U.S. Pat. No. 4,291,298, issued Sept. 22, 1981, I disclosed a codec that requires fewer capacitors. It operates by developing an upper and a lower limit voltage on two capacitors and by averaging those voltages to form a trial voltage that is compared to the input analog voltage. The trial voltage replaces one of the limit voltages in accordance with the comparison, and the averaging and comparing steps are repeated to iteratively bring the trial voltage closer to the analog input voltage.
This codec has the advantage of employing few capacitors but it requires the use of buffer amplifiers to transfer the binary voltages to the averaging means. Unity average gain and zero offset in the buffers must be controlled automatically or by a manual adjustment.